1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device having a recessed channel.
2. Description of the Related Art
Recently, as information technologies such as computers have become widespread, semiconductor technology has developed greatly to improve the reliance, data storage capacity and response speed of semiconductor devices by increasing the degree of integration thereof.
As semiconductor devices have become highly integrated, a size of an active region on which various conductive structures are formed has been gradually reduced, so that a channel length of a MOS transistor may be less than or equal to a few microns in the active region.
When the channel length of a MOS transistor is reduced, a source or drain of the MOS transistor, or a voltage applied to a channel region, may have a much greater effect on the electric field in the channel region. This is widely known as the short channel effect. The short channel effect may be manifested as, for example, a threshold voltage drop. This is because the channel region is much more influenced by electrons in a depletion region, the electric field and the voltage distribution of the source and the drain, as well as the gate voltage, when the gate length is shortened.
A dynamic random access memory (DRAM) generally requires high operation speed and data storage capacity, and thus requires many more unit cells in a wafer. The high integration of the unit cell on the wafer requires shortening the gate length of the DRAM, and the shortened gate length leads to a short channel length. The short channel causes various operation failures such as a dynamic failure and a static refresh failure in the DRAM due to the short channel effect.
A lightly doped source/drain (LDD) structure has been the subject of investigation for reducing the short channel effect. However, the LDD structure has a problem of high drain resistance because the channel region and the drain region become more distant from each other.
A transistor having a recessed channel (hereinafter referred to as a “recessed channel transistor”) has been proposed for reducing the short channel effect without the resistance increase at the drain evident in the LDD structure. In the recessed channel transistor, an active region of the substrate is recessed to a predetermined depth after a device isolation layer is formed in a trench in a field region, and a gate electrode is formed in the recessed portion (hereinafter referred to as a “gate trench”) of the active region. Therefore, a length of the gate electrode is increased without increasing a surface area thereof in a horizontal direction, so that a length of the channel is increased in the recessed channel transistor, while maintaining a small footprint on the substrate.
The design of a recessed channel transistor is such that source and drain regions are formed at surface portions of the substrate symmetrically with respect to the gate electrode. Accordingly, a channel is formed on a portion of sidewalls and a bottom surface of the gate trench in the recessed channel transistor. A remaining portion of the sidewall of the trench that does not make contact with the source/drain regions makes contact with a device isolation layer formed in a trench surrounding an active region. Hereinafter, the trench surrounding the active region is referred to as a “field trench.”
When the silicon substrate in the active region is partially etched away to form the gate trench, there is a problem in that the etching process is prohibited due to the device isolation layer in the field trench. Thus, a boundary portion of the active region between the field trench and the gate trench is not etched away, but rather remains to form a silicon fence. In addition, upper portions of the gate and field trenches end up being larger than lower portions thereof due to imperfections in the anisotropic etching process, so that the silicon fence becomes thicker as the depth of the gate trench is increased.
A parasitic channel is formed along the silicon fence in the recessed channel transistor, so that the recessed channel does not effectively increase the channel length. Thus, failures such as the dynamic failure and static refresh failure discussed above are still generated. Removal of the silicon fence requires additional processing steps, resulting in increased manufacturing costs for semiconductor devices.
Accordingly, there is a need for an improved manufacturing method for a recessed channel transistor that avoids the formation of a silicon fence.